Now showing items 1-20 of 57
Next Page| Abstract: | This paper presents a new approach to implement Reed-Muller Universal Logic Module (RM-ULM) networks with reduced delay and hardware for synthesizing logic functions given in Reed-Muller (RM) form. Replication of single control line RM-ULM is used as the only design unit for defining any logic function. An algorithm is proposed that does exhaustive branching to reduce the number of levels and modules required to implement any logic function in RM form. This approach attains a reduction in delay, and power over other implementations of functions having large number of variables. |
| Description: | NORCHIP Conference, 2005. 23rd |
| URI: | http://dyuthi.cusat.ac.in/purl/3883 |
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| Automated synth ... logic module networks.pdf | (2.066Mb) |
| Abstract: | A new fast stream cipher, MAJE4 is designed and developed with a variable key size of 128-bit or 256-bit. The randomness property of the stream cipher is analysed by using the statistical tests. The performance evaluation of the stream cipher is done in comparison with another fast stream cipher called JEROBOAM. The focus is to generate a long unpredictable key stream with better performance, which can be used for cryptographic applications. |
| Description: | INDICON, 2005 Annual IEEE |
| URI: | http://dyuthi.cusat.ac.in/purl/3865 |
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| A New Fast Stream Cipher MAJE4.pdf | (1.449Mb) |
| Abstract: | This paper discusses the complexities involved in managing and monitoring the delivery of IT services in a multiparty outsourcing environment. The complexities identified are grouped into four categories and are tabulated. A discussion on an attempt to model a multiparty outsourcing scenario using UML is also presented and explained using an illustration. Such a model when supplemented by a performance evaluation tool can enable an organization to manage the provision of IT services in a multiparty outsourcing environment more effectively |
| Description: | CSREA EEE |
| URI: | http://dyuthi.cusat.ac.in/purl/3893 |
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| Analyzing and M ... tsourcing Environment..pdf | (318.9Kb) |
| Abstract: | A novel and fast technique for cryptographic applications is designed and developed using the symmetric key algorithm “MAJE4” and the popular asymmetric key algorithm “RSA”. The MAJE4 algorithm is used for encryption / decryption of files since it is much faster and occupies less memory than RSA. The RSA algorithm is used to solve the problem of key exchange as well as to accomplish scalability and message authentication. The focus is to develop a new hybrid system called MARS4 by combining the two cryptographic methods with an aim to get the advantages of both. The performance evaluation of MARS4 is done in comparison with MAJE4 and RSA. |
| Description: | India Conference, 2006 Annual IEEE |
| URI: | http://dyuthi.cusat.ac.in/purl/3909 |
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| A Novel Fast Hybrid Cryptographic System MARS4.pdf | (191.8Kb) |
| Abstract: | The focus of this work is to provide authentication and confidentiality of messages in a swift and cost effective manner to suit the fast growing Internet applications. A nested hash function with lower computational and storage demands is designed with a view to providing authentication as also to encrypt the message as well as the hash code using a fast stream cipher MAJE4 with a variable key size of 128-bit or 256-bit for achieving confidentiality. Both nested Hash function and MAJE4 stream cipher algorithm use primitive computational operators commonly found in microprocessors; this makes the method simple and fast to implement both in hardware and software. Since the memory requirement is less, it can be used for handheld devices for security purposes. |
| Description: | Advanced Computing and Communications, 2006. ADCOM 2006. International Conference on |
| URI: | http://dyuthi.cusat.ac.in/purl/3881 |
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| Message Integri ... d a Fast Stream Cipher.pdf | (1.288Mb) |
| Abstract: | Sensor networks are one of the fastest growing areas in broad of a packet is in transit at any one time. In GBR, each node in the network can look at itsneighbors wireless ad hoc networking (? Eld. A sensor node, typically'hop count (depth) and use this to decide which node to forward contains signal-processing circuits, micro-controllers and a the packet on to. If the nodes' power level drops below a wireless transmitter/receiver antenna. Energy saving is one certain level it will increase the depth to discourage trafiE of the critical issue for sensor networks since most sensors are equipped with non-rechargeable batteries that have limitedlifetime. Routing schemes are used to transfer data collectedby sensor nodes to base stations. In the literature many routing protocols for wireless sensor networks are suggested. In this work, four routing protocols for wireless sensor networks viz Flooding, Gossiping, GBR and LEACH have been simulated using TinyOS and their power consumption is studied using PowerTOSSIM. A realization of these protocols has beencarried out using Mica2 Motes. |
| Description: | Ad Hoc and Ubiquitous Computing, 2006. ISAUHC'06. International Symposium on |
| URI: | http://dyuthi.cusat.ac.in/purl/3882 |
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| Evaluation of t ... reless Sensor Networks.pdf | (906.1Kb) |
| Abstract: | In a sigma-delta analog to digital (A/D) As most of the sigma-delta ADC applications require converter, the most computationally intensive block is decimation filters with linear phase characteristics, the decimation filter and its hardware implementation symmetric Finite Impulse Response (FIR) filters are may require millions of transistors. Since these widely used for implementation. But the number of FIR converters are now targeted for a portable application, filter coefficients will be quite large for implementing a a hardware efficient design is an implicit requirement. narrow band decimation filter. Implementing decimation In this effect, this paper presents a computationally filter in several stages reduces the total number of filter efficient polyphase implementation of non-recursive coefficients, and hence reduces the hardware complexity cascaded integrator comb (CIC) decimators for and power consumption [2]. Sigma-Delta Converters (SDCs). The SDCs are The first stage of decimation filter can be operating at high oversampling frequencies and hence implemented very efficiently using a cascade of integrators require large sampling rate conversions. The filtering and comb filters which do not require multiplication or and rate reduction are performed in several stages to coefficient storage. The remaining filtering is performed reduce hardware complexity and power dissipation. either in single stage or in two stages with more complex The CIC filters are widely adopted as the first stage of FIR or infinite impulse response (IIR) filters according to decimation due to its multiplier free structure. In this the requirements. The amount of passband aliasing or research, the performance of polyphase structure is imaging error can be brought within prescribed bounds by compared with the CICs using recursive and increasing the number of stages in the CIC filter. The non-recursive algorithms in terms of power, speed and width of the passband and the frequency characteristics area. This polyphase implementation offers high speed outside the passband are severely limited. So, CIC filters operation and low power consumption. The polyphase are used to make the transition between high and low implementation of 4th order CIC filter with a sampling rates. Conventional filters operating at low decimation factor of '64' and input word length of sampling rate are used to attain the required transition '4-bits' offers about 70% and 37% of power saving bandwidth and stopband attenuation. compared to the corresponding recursive and Several papers are available in literature that deals non-recursive implementations respectively. The same with different implementations of decimation filter polyphase CIC filter can operate about 7 times faster architecture for sigma-delta ADCs. Hogenauer has than the recursive and about 3.7 times faster than the described the design procedures for decimation and non-recursive CIC filters. |
| Description: | Electron Devices and Solid-State Circuits, 2007. EDSSC 2007. IEEE Conference on |
| URI: | http://dyuthi.cusat.ac.in/purl/3858 |
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| Polyphase Implementation of Non-recursive Comb.pdf | (4.781Mb) |
| Abstract: | In this paper we discuss our research in developing general and systematic method for anomaly detection. The key ideas are to represent normal program behaviour using system call frequencies and to incorporate probabilistic techniques for classification to detect anomalies and intrusions. Using experiments on the sendmail system call data, we demonstrate that we can construct concise and accurate classifiers to detect anomalies. We provide an overview of the approach that we have implemented |
| Description: | Availability, Reliability and Security, 2007. ARES 2007. The Second International Conference on |
| URI: | http://dyuthi.cusat.ac.in/purl/3864 |
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| Process Profili ... encies of System Calls.pdf | (268.7Kb) |
| Abstract: | This paper presents a performance analysis of reversible, fault tolerant VLSI implementations of carry select and hybrid decimal adders suitable for multi-digit BCD addition. The designs enable partial parallel processing of all digits that perform high-speed addition in decimal domain. When the number of digits is more than 25 the hybrid decimal adder can operate 5 times faster than conventional decimal adder using classical logic gates. The speed up factor of hybrid adder increases above 10 when the number of decimal digits is more than 25 for reversible logic implementation. Such highspeed decimal adders find applications in real time processors and internet-based applications. The implementations use only reversible conservative Fredkin gates, which make it suitable for VLSI circuits. |
| Description: | Proceedings of the World Congress on Engineering and Computer Science 2007 WCECS 2007, October 24-26, 2007, San Francisco, USA |
| URI: | http://dyuthi.cusat.ac.in/purl/3891 |
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| Performance Ana ... le Fast Decimal Adders.pdf | (402.4Kb) |
| Abstract: | Residue Number System (RNS) based Finite Impulse Response (FIR) digital filters and traditional FIR filters. This research is motivated by the importance of an efficient filter implementation for digital signal processing. The comparison is done in terms of speed and area requirement for various filter specifications. RNS based FIR filters operate more than three times faster and consumes only about 60% of the area than traditional filter when number of filter taps is more than 32. The area for RNS filter is increasing at a lesser rate than that for traditional resulting in lower power consumption. RNS is a nonweighted number system without carry propogation between different residue digits.This enables simultaneous parallel processing on all the digits resulting in high speed addition and multiplication in the RNS domain |
| Description: | Communications and Information Technologies, 2007. ISCIT'07. International Symposium on |
| URI: | http://dyuthi.cusat.ac.in/purl/3861 |
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| Performance ana ... RNS versus traditional.pdf | (257.8Kb) |
| Abstract: | In recent years, reversible logic has emerged as one of the most important approaches for power optimization with its application in low power CMOS, quantum computing and nanotechnology. Low power circuits implemented using reversible logic that provides single error correction – double error detection (SEC-DED) is proposed in this paper. The design is done using a new 4 x 4 reversible gate called ‘HCG’ for implementing hamming error coding and detection circuits. A parity preserving HCG (PPHCG) that preserves the input parity at the output bits is used for achieving fault tolerance for the hamming error coding and detection circuits. |
| Description: | TENCON 2007-2007 IEEE Region 10 Conference |
| URI: | http://dyuthi.cusat.ac.in/purl/3859 |
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| Fault Tolerant ... ng and Detection using.pdf | (168.5Kb) |
| Abstract: | Reversibility plays a fundamental role when logic gates such as AND, OR, and XOR are not reversible. computations with minimal energy dissipation are considered. Hence, these gates dissipate heat and may reduce the life of In recent years, reversible logic has emerged as one of the most the circuit. So, reversible logic is in demand in power aware important approaches for power optimization with its circuits. application in low power CMOS, quantum computing and A reversible conventional BCD adder was proposed in using conventional reversible gates. |
| Description: | System-on-Chip, 2007 International Symposium on |
| URI: | http://dyuthi.cusat.ac.in/purl/3863 |
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| A new look at r ... ation of decimal adder.pdf | (344.1Kb) |
| Abstract: | This paper discusses our research in developing a generalized and systematic method for anomaly detection. The key ideas are to represent normal program behaviour using system call frequencies and to incorporate probabilistic techniques for classification to detect anomalies and intrusions. Using experiments on the sendmail system call data, we demonstrate that concise and accurate classifiers can be constructed to detect anomalies. An overview of the approach that we have implemented is provided. |
| Description: | JOURNAL OF SOFTWARE, VOL. 2, NO. 6, DECEMBER 2007 |
| URI: | http://dyuthi.cusat.ac.in/purl/3866 |
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| Anomaly Detection Using System Call.pdf | (312.1Kb) |
| Abstract: | In recent years, reversible logic has emerged as one of the most important approaches for power optimization with its application in low power CMOS, nanotechnology and quantum computing. This research proposes quick addition of decimals (QAD) suitable for multi-digit BCD addition, using reversible conservative logic. The design makes use of reversible fault tolerant Fredkin gates only. The implementation strategy is to reduce the number of levels of delay there by increasing the speed, which is the most important factor for high speed circuits. |
| Description: | Advanced Computing and Communications, 2007. ADCOM 2007. International Conference on |
| URI: | http://dyuthi.cusat.ac.in/purl/3876 |
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| Quick Addition ... ble Conservative Logic.pdf | (264.0Kb) |
| Abstract: | This paper describes JERIM-320, a new 320-bit hash function used for ensuring message integrity and details a comparison with popular hash functions of similar design. JERIM-320 and FORK -256 operate on four parallel lines of message processing while RIPEMD-320 operates on two parallel lines. Popular hash functions like MD5 and SHA-1 use serial successive iteration for designing compression functions and hence are less secure. The parallel branches help JERIM-320 to achieve higher level of security using multiple iterations and processing on the message blocks. The focus of this work is to prove the ability of JERIM 320 in ensuring the integrity of messages to a higher degree to suit the fast growing internet applications |
| Description: | International Journal of Computer Science and Applications, Vol. 5, No. 4, pp 11 - 25, 2008 |
| URI: | http://dyuthi.cusat.ac.in/purl/4021 |
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| Jerim-320 A New ... With Parallel Branches.pdf | (96.80Kb) |
| Abstract: | Cluster based protocols like LEACH were found best suited for routing in wireless sensor networks. In mobility centric environments some improvements were suggested in the basic scheme. LEACH-Mobile is one such protocol. The basic LEACH protocol is improved in the mobile scenario by ensuring whether a sensor node is able to communicate with its cluster head. Since all the nodes, including cluster head is moving it will be better to elect a node as cluster head which is having less mobility related to its neighbours. In this paper, LEACH-Mobile protocol has been enhanced based on a mobility metric “remoteness” for cluster head election. This ensures high success rate in data transfer between the cluster head and the collector nodes even though nodes are moving. We have simulated and compared our LEACH-Mobile-Enhanced protocol with LEACHMobile. Results show that inclusion of neighbouring node information improves the routing protocol. |
| Description: | ADCOM 2008 |
| URI: | http://dyuthi.cusat.ac.in/purl/3857 |
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| Mobility Metric based LEACH-Mobile Protocol.pdf | (272.3Kb) |
| Abstract: | Extensive use of the Internet coupled with the marvelous growth in e-commerce and m-commerce has created a huge demand for information security. The Secure Socket Layer (SSL) protocol is the most widely used security protocol in the Internet which meets this demand. It provides protection against eaves droppings, tampering and forgery. The cryptographic algorithms RC4 and HMAC have been in use for achieving security services like confidentiality and authentication in the SSL. But recent attacks against RC4 and HMAC have raised questions in the confidence on these algorithms. Hence two novel cryptographic algorithms MAJE4 and MACJER-320 have been proposed as substitutes for them. The focus of this work is to demonstrate the performance of these new algorithms and suggest them as dependable alternatives to satisfy the need of security services in SSL. The performance evaluation has been done by using practical implementation method. |
| URI: | http://dyuthi.cusat.ac.in/xmlui/purl/2077 |
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| Use of novel algorithms MAJE4 and MACJER-320...pdf | (326.2Kb) |
| Abstract: | The recent trends envisage multi-standard architectures as a promising solution for the future wireless transceivers to attain higher system capacities and data rates. The computationally intensive decimation filter plays an important role in channel selection for multi-mode systems. An efficient reconfigurable implementation is a key to achieve low power consumption. To this end, this paper presents a dual-mode Residue Number System (RNS) based decimation filter which can be programmed for WCDMA and 802.16e standards. Decimation is done using multistage, multirate finite impulse response (FIR) filters. These FIR filters implemented in RNS domain offers high speed because of its carry free operation on smaller residues in parallel channels. Also, the FIR filters exhibit programmability to a selected standard by reconfiguring the hardware architecture. The total area is increased only by 24% to include WiMAX compared to a single mode WCDMA transceiver. In each mode, the unused parts of the overall architecture is powered down and bypassed to attain power saving. The performance of the proposed decimation filter in terms of critical path delay and area are tabulated. |
| Description: | Vehicular Technology Conference, 2008. VTC Spring 2008. IEEE |
| URI: | http://dyuthi.cusat.ac.in/purl/3869 |
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| RNS based Programmable Multi-mode Decimation.pdf | (293.6Kb) |
| Abstract: | The recent trends envisage multi-standard architectures as a promising solution for the future wireless transceivers. The computationally intensive decimation filter plays an important role in channel selection for multi-mode systems. An efficient reconfigurable implementation is a key to achieve low power consumption. To this end, this paper presents a dual-mode Residue Number System (RNS) based decimation filter which can be programmed for WCDMA and 802.11a standards. Decimation is done using multistage, multirate finite impulse response (FIR) filters. These FIR filters implemented in RNS domain offers high speed because of its carry free operation on smaller residues in parallel channels. Also, the FIR filters exhibit programmability to a selected standard by reconfiguring the hardware architecture. The total area is increased only by 33% to include WLANa compared to a single mode WCDMA transceiver. In each mode, the unused parts of the overall architecture is powered down and bypassed to attain power saving. The performance of the proposed decimation filter in terms of critical path delay and area are tabulated |
| Description: | Circuits and Systems, 2008. ISCAS 2008. IEEE International Symposium on Pages 952-955 |
| URI: | http://dyuthi.cusat.ac.in/purl/3875 |
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| Dual-Mode RNS based Programmable Decimation.pdf | (177.9Kb) |
| Abstract: | Extensive use of the Internet coupled with the marvelous growth in e-commerce and m-commerce has created a huge demand for information security. The Secure Socket Layer (SSL) protocol is the most widely used security protocol in the Internet which meets this demand. It provides protection against eaves droppings, tampering and forgery. The cryptographic algorithms RC4 and HMAC have been in use for achieving security services like confidentiality and authentication in the SSL. But recent attacks against RC4 and HMAC have raised questions in the confidence on these algorithms. Hence two novel cryptographic algorithms MAJE4 and MACJER-320 have been proposed as substitutes for them. The focus of this work is to demonstrate the performance of these new algorithms and suggest them as dependable alternatives to satisfy the need of security services in SSL. The performance evaluation has been done by using practical implementation method. |
| Description: | World Academy of Science, Engineering and Technology Vol:2 2008-03-28 |
| URI: | http://dyuthi.cusat.ac.in/purl/3880 |
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| Use of Novel Al ... tication in SSL & TLS..pdf | (125.4Kb) |
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