Poulose Jacob,K; Shahana, T K; Babita, Jose R; Sreela Sasi(Taylor & Francis, May 1, 2009)
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Abstract:
Animportant step in the residue number system(RNS) based signal processing is the
conversion of signal into residue domain. Many implementations of this conversion
have been proposed for various goals, and one of the implementations is by a direct
conversion from an analogue input. A novel approach for analogue-to-residue
conversion is proposed in this research using the most popular Sigma–Delta
analogue-to-digital converter (SD-ADC). In this approach, the front end is the same
as in traditional SD-ADC that uses Sigma–Delta (SD) modulator with appropriate
dynamic range, but the filtering is doneby a filter implemented usingRNSarithmetic.
Hence, the natural output of the filter is an RNS representation of the input signal.
The resolution, conversion speed, hardware complexity and cost of implementation
of the proposed SD based analogue-to-residue converter are compared with the
existing analogue-to-residue converters based on Nyquist rate ADCs
Description:
International Journal of Electronics
Vol. 96, No. 6, June 2009, 571–583
Poulose Jacob,K; Rekha, James K; Sreela Sasi; Shahana, T K; Babita, Jose R(IEEE, May 11, 2008)
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Abstract:
The recent trends envisage multi-standard
architectures as a promising solution for the future wireless
transceivers to attain higher system capacities and data rates.
The computationally intensive decimation filter plays an
important role in channel selection for multi-mode systems. An
efficient reconfigurable implementation is a key to achieve low
power consumption. To this end, this paper presents a dual-mode
Residue Number System (RNS) based decimation filter which can
be programmed for WCDMA and 802.16e standards. Decimation
is done using multistage, multirate finite impulse response (FIR)
filters. These FIR filters implemented in RNS domain offers high
speed because of its carry free operation on smaller residues in
parallel channels. Also, the FIR filters exhibit programmability
to a selected standard by reconfiguring the hardware
architecture. The total area is increased only by 24% to include
WiMAX compared to a single mode WCDMA transceiver. In
each mode, the unused parts of the overall architecture is
powered down and bypassed to attain power saving. The
performance of the proposed decimation filter in terms of critical
path delay and area are tabulated.
Description:
Vehicular Technology Conference, 2008. VTC Spring 2008. IEEE