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| Abstract: | This paper presents a new approach to implement Reed-Muller Universal Logic Module (RM-ULM) networks with reduced delay and hardware for synthesizing logic functions given in Reed-Muller (RM) form. Replication of single control line RM-ULM is used as the only design unit for defining any logic function. An algorithm is proposed that does exhaustive branching to reduce the number of levels and modules required to implement any logic function in RM form. This approach attains a reduction in delay, and power over other implementations of functions having large number of variables. |
| Description: | NORCHIP Conference, 2005. 23rd |
| URI: | http://dyuthi.cusat.ac.in/purl/3883 |
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| Automated synth ... logic module networks.pdf | (2.066Mb) |
| Abstract: | Residue Number System (RNS) based Finite Impulse Response (FIR) digital filters and traditional FIR filters. This research is motivated by the importance of an efficient filter implementation for digital signal processing. The comparison is done in terms of speed and area requirement for various filter specifications. RNS based FIR filters operate more than three times faster and consumes only about 60% of the area than traditional filter when number of filter taps is more than 32. The area for RNS filter is increasing at a lesser rate than that for traditional resulting in lower power consumption. RNS is a nonweighted number system without carry propogation between different residue digits.This enables simultaneous parallel processing on all the digits resulting in high speed addition and multiplication in the RNS domain |
| Description: | Communications and Information Technologies, 2007. ISCIT'07. International Symposium on |
| URI: | http://dyuthi.cusat.ac.in/purl/3861 |
| Files | Size |
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| Performance ana ... RNS versus traditional.pdf | (257.8Kb) |
| Abstract: | In recent years, reversible logic has emerged as one of the most important approaches for power optimization with its application in low power CMOS, nanotechnology and quantum computing. This research proposes quick addition of decimals (QAD) suitable for multi-digit BCD addition, using reversible conservative logic. The design makes use of reversible fault tolerant Fredkin gates only. The implementation strategy is to reduce the number of levels of delay there by increasing the speed, which is the most important factor for high speed circuits. |
| Description: | Advanced Computing and Communications, 2007. ADCOM 2007. International Conference on |
| URI: | http://dyuthi.cusat.ac.in/purl/3876 |
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| Quick Addition ... ble Conservative Logic.pdf | (264.0Kb) |
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